Workshop & Tutorial Details

Advanced Design, Analysis and Verification of NoC Architectures (NoC)

9:00 - 9:15Introduction and Overview
Dr. Mandy Pant (Intel Corp.), Umit Ogras (Arizona State University)

9:15 - 9:45Architectural Exploration and Physical Planning of Hierarchical Tiled CMPs
Jordi Cortadella (UPC Barcelona)

9:45 - 10:15Accelerating Many-Core Network-on-Chip Simulation
Natalie Enright-Jerger (University of Toronto)

10:15 - 10:45Synergistic Power Management and QoS in future Chip-Multiprocessors
Prof. Gratz (University of Texas A&M)

10:45 - 11:00Break

11:00 - 11:30Implicit and Explicit Heterogeneity in Power Aware High Performance Multi-Core Systems
Diana Marculescu (Carnegie Mellon University)

11:30 - 12:00Formal Verification of On-Chip Communication Fabrics
Julien Schmaltz (OUN The Netherlands)

12:00 - 12:30Towards micro-architectural model QoS analysis
Zhonghai Lu, Axel Jantsch (KTH Sweden)

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